In most computer systems, the function of communications between different components is typically performed by a bus. The bus architecture is designed to be well established and portable such that it can be utilized in multiple configurations without excessive additional development expenses when designing for derivative products. In addition, a bus is designed to perform high-speed communication processing to support increase in frequency of a processor's clock.
An application specific integrated circuit (ASIC) typically includes one or more core processors, one or more memory units, and other functional modules, all integrated on a single semiconductor ASIC (or chip). Having the modules on the same ASIC allows data to be easily and quickly transferred between the various modules. To provide high speed data transfers on an ASIC, specialized internal buses are designed specifically for this purpose. One example for such a specialized bus is the advanced high-performance bus (AHB), developed by ARM™ Ltd. The AHB operates in accordance with the advanced microcontroller bus architecture (AMBA) protocol and provides high-speed data transfers between various components on an ASIC. Another example is the advanced peripheral bus (APB), which provides the basic peripheral macro-cell communication infrastructure as a secondary bus from the higher bandwidth pipelined main system bus. The APB is designed to reduce interface complexity for supporting of peripheral functions. The limitations of the AHB, APB in addition to other types of internal buses are the inability to support inter-connection and inter-communication between the various modules on an ASIC.
Specifically, various modules of the ASIC typically operate at different clock frequencies. To support efficient inter-connection and inter-communication between such modules, there is a need to synchronize data transfers over the internal bus.
A straightforward approach for transferring data directly from a low-frequency module to a high-frequency module would result in low utilization of the bus, as the bus would be operative only when the low-frequency clock is active. In addition, transferring data from a high-frequency module to a low-frequency module without any synchronization means would result in losing data.
Therefore, it would be advantageous to provide an internal bus' frequency adapter to ensure efficient inter-connection and inter-communication among modules connected to the bus.